; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from IPI-U05.jed. Date: 2012-10-28
;
; Application connector address decoder
;
; Address 0Fxxx is decoded into several 16-byte blocks
; in memory and I/O space.
; Outputs got to the application connector PL2
; The manual does not mention what they are used for,
; presumably application-specific.
;

chip IPI-U05 PAL20L10

a16=1	;
a15=2	;
a14=3	;
a13=4	;
a12=5	;
a6=6	;
a5=7	;
a4=8	;
/IORQ=9	;
/MREQ=10	;
/RD=11	;
GND=12	;
/WR=13	;

/Fx0x_RD=14	;
/Fx0x_WR=15	;
/Fx1x_WR=16	;
/Fx2x_RD=17	;
/Fx2x_WR=18	;
/Fx3x_WR=19	;
/Fx4x_RD=20	;
/Fx4x_WR=21	;
/Fx7x_WR=22	;
VCC=24 

equations

; intermediate terms

address_0Fxxx	=	/a16 * a15 * a14 * a13 * a12
MEM_RD	=	MREQ * RD
MEM_WR	=	MREQ * WR
IO_RD	=	IORQ * RD
IO_WR	=	IORQ * WR

offset_00h	=	/a6 * /a5 * /a4
offset_10h	=	/a6 * /a5 *  a4
offset_20h	=	/a6 *  a5 * /a4
offset_30h	=	/a6 *  a5 *  a4
offset_40h	=	 a6 * /a5 * /a4
offset_50h	=	 a6 * /a5 *  a4	; unused
offset_60h	=	 a6 *  a5 * /a4	; unused
offset_70h	=	 a6 *  a5 *  a4

;
; output pins activate at same address in Z180 memory or I/O space:
;
Fx0x_RD	=	 address_0Fxxx * offset_00h	*	IO_RD
	+	 address_0Fxxx * offset_00h	*	MEM_RD

Fx0x_WR	=	 address_0Fxxx * offset_00h	*	IO_WR
	+	 address_0Fxxx * offset_00h	*	MEM_WR
	+	 address_0Fxxx * offset_70h	*	MEM_WR

Fx1x_WR	=	 address_0Fxxx * offset_10h	*	IO_WR
	+	 address_0Fxxx * offset_10h	*	MEM_WR

Fx2x_RD	=	 address_0Fxxx * offset_20h	*	IO_RD
	+	 address_0Fxxx * offset_20h	*	MEM_RD

Fx2x_WR	=	 address_0Fxxx * offset_20h	*	IO_WR
	+	 address_0Fxxx * offset_20h	*	MEM_WR
	+	 address_0Fxxx * offset_70h	*	MEM_WR

Fx3x_WR	=	 address_0Fxxx * offset_30h	*	IO_WR
	+	 address_0Fxxx * offset_30h	*	MEM_WR

Fx4x_RD	=	 address_0Fxxx * offset_40h	*	IO_RD
	+	 address_0Fxxx * offset_40h	*	MEM_RD

Fx4x_WR	=	 address_0Fxxx * offset_40h	*	IO_WR
	+	 address_0Fxxx * offset_40h	*	MEM_WR
	+	 address_0Fxxx * offset_70h	*	MEM_WR

Fx7x_WR	=	 address_0Fxxx * offset_70h	*	IO_WR
	+	 address_0Fxxx * offset_70h	*	MEM_WR	; also selects Fx0x, Fx2x, Fx4x

Fx7x_WR.oe	=	vcc
Fx4x_WR.oe	=	vcc
/Fx4x_RD.oe	=	vcc
/Fx3x_WR.oe	=	vcc
/Fx2x_WR.oe	=	vcc
/Fx2x_RD.oe	=	vcc
/Fx1x_WR.oe	=	vcc
/Fx0x_WR.oe	=	vcc
/Fx0x_RD.oe	=	vcc